 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| october 2006 rev 9 1/53 1 m50fw040 4-mbit (512 kb x8, uniform block) 3-v supply firmware hub flash memory feature summary supply voltage ?v cc = 3 v to 3.6 v for program, erase and read operations ?v pp = 12v for fast erase (optional) two interfaces ? firmware hub (fwh) interface for embedded operation with pc chipsets ? address/address multiplexed (a/a mux) interface for programming equipment compatibility firmware hub (fwh) hardware interface mode ? 5-signal communication interface supporting read and write operations ? hardware write protect pins for block protection ? register based read and write protection ? 5 additional general-purpose inputs for platform design flexibility ? synchronized with 33-mhz pci clock programming time: 10 s typical 8 uniform 64 kbyte memory blocks program/erase controller ? embedded byte program and block erase algorithms ? status register bits program and erase suspend ? read other blocks during program/erase suspend ? program other blocks during erase suspend for use in pc bios applications electronic signature ? manufacturer code: 20h ? device code: 2ch packages ? ecopack? (rohs compliant) tsop40 (n) 10 20mm plcc32 (k) tsop32 (nb) 8 14mm www.st.com
contents m50fw040 2/53 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 firmware hub (fwh) signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 input/output communications (fwh0-fwh3) . . . . . . . . . . . . . . . . . . . . 12 2.1.2 input communication frame (fwh4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.3 identification inputs (id0-id3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.4 general-purpose inputs (fgpi0-fgpi4) . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.5 interface configuration (ic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.6 interface reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.7 cpu reset (init ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.8 clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.9 top block lock (tbl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.10 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.11 reserved for future use (rfu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 address/address multiplexed (a/a mux) si gnal descriptions . . . . . . . . . . 14 2.2.1 address inputs (a0-a10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.4 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.5 row/column address select (rc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.6 ready/busy output (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 v pp optional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 firmware hub (fwh) bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.3 bus abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 m50fw040 contents 3/53 3.1.6 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 address/address multiplexed (a/a mux) bus operations . . . . . . . . . . . . . 19 3.2.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0.1 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0.2 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0.3 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0.4 program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0.5 v pp status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.0.6 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.0.7 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.0.8 reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 firmware hub (fwh) interface configuration registers . . . . . . . . . . . 30 6.1 lock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.1 write lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.2 read lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.3 lock down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 firmware hub (fwh) general-purpose input register . . . . . . . . . . . . . . 31 6.3 manufacturer code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 device code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.5 firmware hub (fwh) general-purpose input register . . . . . . . . . . . . . . 31 contents m50fw040 4/53 6.6 manufacturer code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.7 device code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 program and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12 flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 m50fw040 list of tables 5/53 list of tables table 1. signal names (fwh interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. signal names (a/a mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. fwh bus read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. fwh bus write field definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. firmware hub configuration register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. lock register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. general-purpose input register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12. program and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. fwh interface ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. a/a mux interface ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. fwh interface clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. fwh interface ac signal timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 22. a/a mux interface read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 23. a/a mux interface write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 25. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 26. tsop40 ? 40 lead plastic thin small outline, 10x20 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 27. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 list of figures m50fw040 6/53 list of figures figure 1. logic diagram (fwh interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. logic diagram (a/a mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. plcc connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. tsop32 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. tsop40 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. fwh bus read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. fwh bus write waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. fwh interface ac testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. a/a mux interface ac testing input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 10. fwh interface clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. fwh interface ac signal timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. a/a mux interface read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14. a/a mux interface write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package outline . . . . . . . . . . 44 figure 16. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package outline . . . . . . . . . . . . 45 figure 17. tsop40 ? 40 lead plastic thin small outline, 10x20 mm, package outline . . . . . . . . . . . 46 figure 18. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 figure 19. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 20. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 21. erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 m50fw040 summary description 7/53 1 summary description the m50fw040 is a 4 mbit (512kb x8) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (3.0 to 3.6v) supply. for fast erasing in production lines an optional 12v power supply can be used to reduce the erasing time. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. blocks can be protected individually to prevent accidental program or erase commands from modifying the memory. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memo ry is consistent with jedec standards. two different bus interfaces are supported by the memory. the primary interface, the firmware hub (or fwh) interface, uses intel?s proprietary fwh protocol. this has been designed to remove the need for the isa bus in current pc chipsets; the m50fw040 acts as the pc bios on the low pin count bus for these pc chipsets. the secondary interface, the address/address multiplexed (or a/a mux) interface, is designed to be compatible with current flash programmers for production line programming prior to fitting to a pc motherboard. the memory is offered in tsop32 (8 x 14mm), tsop40 (10 x 20mm) and plcc32 packages and it is supplied with all the bits erased (set to ?1?). in order to meet environmental requirements, st offers the m50fw040 in ecopack? packages. ecopack? packages are lead-free and rohs compliant. ecopack is an st trademark. ecopack specifications are available at: www.st.com . summary description m50fw040 8/53 figure 1. logic diagram (fwh interface) table 1. signal names (fwh interface) fwh0-fwh3 input/out put communications fwh4 input communication frame id0-id3 identif ication inputs fgpi0-fgpi4 general purpose inputs ic interface configuration rp interface reset init cpu reset clk clock tbl top block lock wp write protect rfu reserved for future use. leave disconnected v cc supply voltage v pp optional supply voltage for fast erase operations v ss ground nc not connected internally ai03623 4 fwh4 fwh0- fwh3 v cc m50fw040 clk v ss 4 ic rp tbl 5 init wp id0-id3 fgpi0- fgpi4 v pp m50fw040 summary description 9/53 figure 2. logic diagram (a/a mux interface) table 2. signal names (a/a mux interface) ic interface configuration a0-a10 address inputs dq0-dq7 data inputs/outputs g output enable w write enable rc row/column address select rb ready/busy output rp interface reset v cc supply voltage v pp optional supply voltage for fast program and erase operations v ss ground nc not connected internally ai10719 11 rc dq0-dq7 v cc m50fw040 ic v ss 8 g w rb rp a0-a10 v pp summary description m50fw040 10/53 figure 3. plcc connections 1. pins 27 and 28 are not internally connected. figure 4. tsop32 connections 1. the rb pin is not available for the a/a mux interface in the tsop32 package. ai03616 fgpi4 nc fwh4 rfu 17 id1 id0 fwh0 fwh1 fwh2 fwh3 rfu fgpi1 tbl id3 id2 fgpi0 wp 9 clk v ss 1 rp v cc nc fgpi2 rfu 32 v pp v cc m50fw040 fgpi3 ic (v il ) rfu init rfu 25 v ss a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 rc rp a8 v pp v cc a9 nc w v ss v cc nc dq7 ic (v ih ) g rb dq5 dq1 dq2 dq3 dq4 dq6 v ss a/a mux a/a mux a/a mux a/a mux ai10718 a1 a0 dq0 a7 a4 a3 a2 a6 a5 a9 a8 w dq7 g nc dq5 dq1 dq2 dq3 dq4 dq6 a/a mux a/a mux id1 fwh1/lad1 fwh2/lad2 gpi3 tbl id2 gpi0 wp nc nc rfu gpi4 nc fwh4/lframe rfu fwh3/lad3 v ss rfu rfu clk rp v pp v cc m50fw040 8 1 9 16 17 24 25 32 id3/rfu v ss init ic nc gpi2 fwh0/lad0 gpi1 id0 nc nc ic (v ih ) nc nc rc rp v pp v cc a10 v ss m50fw040 summary description 11/53 figure 5. tsop40 connections ai03617 a1 a0 dq0 a7 a4 a3 a2 a6 a5 a9 a8 w v ss v cc dq7 g rb dq5 dq1 dq2 dq3 dq4 dq6 a/a mux a/a mux id1 fwh1 fwh2 fgpi3 tbl id2 fgpi0 wp nc v cc nc ic (v il ) rfu fgpi4 nc v ss fwh4 rfu fwh3 v ss v cc rfu rfu nc clk rp nc v pp v cc nc m50fw040 10 1 11 20 21 30 31 40 id3 nc init nc rfu fgpi2 fwh0 fgpi1 id0 v ss nc nc nc ic (v ih ) nc nc nc nc rc rp v pp v cc nc a10 v ss v ss v cc signal descriptions m50fw040 12/53 2 signal descriptions there are two different bus interfaces available on this part. the active interface is selected before power-up or during reset using the interface configuration pin, ic. the signals for each interface are discussed in the firmware hub (fwh) signal descriptions section and the address/address multiplexed (a/a mux) signal descriptions section below. the supply signals are discussed in the supply signal descriptions section below. 2.1 firmware hub (fwh ) signal descriptions for the firmware hub (fwh) interface see m50fw040 signal descriptions 13/53 2.1.5 interface configuration (ic) the interface configuration input selects whether the firmware hub (fwh) or the address/address multiplexed (a/a mux) interface is used. the chosen interface must be selected before power-up or during a reset and, thereafter, cannot be changed. the state of the interface configuration, ic, should not be changed during operation. to select the firmware hub (fwh) interface the interface configuration pin should be left to float or driven low, v il ; to select the address/address multiplexed (a/a mux) interface the pin should be driven high, v ih . an internal pull-down resistor is included with a value of r il ; there will be a leakage current of i li2 through each pin when pulled to v ih ; see signal descriptions m50fw040 14/53 2.1.10 write protect (wp ) the write protect input is used to prevent the main blocks (blocks 0 to 6) from being changed. when write protect, wp , is set low, v il , program and erase operations in the main blocks have no effect, regardless of the state of the lock register. when write protect, wp , is set high, v ih , the protection of the block determined by the lock register. the state of write protect, wp , does not affect the protection of the top block (block 7). write protect, wp , must be set prior to a program or erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. care should be taken to avoid unpredictable behavior by changing wp during program or erase suspend. 2.1.11 reserved fo r future use (rfu) these pins do not have assigned functions in th is revision of the part. they must be left disconnected. 2.2 address/address multiplexed (a/a mux) signal descriptions for the address/address multiplexed (a/a mux) interface see m50fw040 signal descriptions 15/53 2.2.6 ready/busy output (rb ) the ready/busy pin gives the status of the memory?s program/erase controller. when ready/busy is low, v ol , the memory is busy with a progra m or erase operation and it will not accept any additional program or erase command except the program/erase suspend command. when ready/busy is high, v oh , the memory is ready for any read, program or erase operation. 2.3 supply signal descriptions the supply signals are the same for both interfaces. 2.3.1 v cc supply voltage the v cc supply voltage supplies the power for all operations (read, program, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. after v cc becomes valid the command interface is reset to read mode. a 0.1f capacitor should be connected between the v cc supply voltage pins and the v ss ground pin to decouple the current surges from the power supply. both v cc supply voltage pins must be connected to the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. 2.3.2 v pp optional supply voltage the v pp optional supply voltage pin is used to select the fast erase option of the memory and to protect the memory. when v pp < v pplk program and erase operations cannot be performed and an error is reported in the status register if an attempt to change the memory contents is made. when v pp = v cc program and erase operations take place as normal. when v pp = v pph fast erase operations are used. any other voltage input to v pp will result in undefined behavi or and should not be used. v pp should not be set to v pph for more than 80 hours during the life of the memory. 2.3.3 v ss ground v ss is the reference for all the voltage measurements. signal descriptions m50fw040 16/53 table 3. block addresses size (kbytes) address range block number block type 64 70000h-7ffffh 7 top block 64 60000h-6ffffh 6 main block 64 50000h-5ffffh 5 main block 64 40000h-4ffffh 4 main block 64 30000h-3ffffh 3 main block 64 20000h-2ffffh 2 main block 64 10000h-1ffffh 1 main block 64 00000h-0ffffh 0 main block m50fw040 bus operations 17/53 3 bus operations the two interfaces have similar bus operations but the signals and timings are completely different. the firmware hub (fwh) interface is the usual interface and all of the functionality of the part is available through this interface. only a subset of functions are available through the address/address multiplexed (a/a mux) interface. follow the section firmware hub (fwh) bus operations below and the section address/address multiplexed (a/a mux) bus operations below for a description of the bus operations on each interface. 3.1 firmware hub (fwh) bus operations the firmware hub (fwh) interface consists of four data signals (fwh0-fwh3), one control line (fwh4) and a clock (clk). in addition prot ection against accidental or malicious data corruption can be achieved using two further signals (tbl and wp ). finally two reset signals (rp and init ) are available to put the memory into a known state. the data signals, control signal and clock are designed to be compatible with pci electrical specifications. the interface operates with clock speeds up to 33mhz. the following operations can be performed using the appropriate bus cycles: bus read, bus write, standby, reset and block protection. 3.1.1 bus read bus read operations read from the memory cells, specific registers in the command interface or firmware hub registers. a valid bus read operation starts when input communication frame, fwh4, is low, v il , as clock rises and the correct start cycle is on fwh0-fwh3. on the following clock cycles the host will send the memory id select, address and other control bits on fwh0-fwh3. the memory responds by outputting sync data until the wait-states have elapsed followed by data0-data3 and data4-data7. refer to table 4: fwh bus read field definitions , and figure 6: fwh bus read waveforms , for a description of the field definitions for each clock cycle of the transfer. see table 20: fwh interface ac signal timing characteristics , and figure 11: fwh interface ac signal timing waveforms , for details on the timings of the signals. 3.1.2 bus write bus write operations write to the command interface or firmware hub registers. a valid bus write operation starts when input communication frame, fwh4, is low, v il , as clock rises and the correct start cycle is on fwh0-f wh3. on the following clock cycles the host will send the memory id select, address, othe r control bits, data0- data3 and da ta4-data7 on fwh0-fwh3. the memory outputs sync data until the wait-states have elapsed. refer to table 5: fwh bus write field definitions , and figure 7: fwh bus write waveforms , for a description of the field definitions for each clock cycle of the transfer. see table 20: fwh interface ac signal timing characteristics , and figure 11: fwh interface ac signal timing waveforms , for details on the timings of the signals. bus operations m50fw040 18/53 3.1.3 bus abort the bus abort operation can be used to immediately abort the current bus operation. a bus abort occurs when fwh4 is driven low, v il , during the bus operation; the memory will tri- state the input/output communication pins, fwh0-fwh3. note that, during a bus write operation, the command interface starts executing the command as soon as the data is fully received; a bus abort during the final tar cycles is not guaranteed to abort the command; the bus, however, will be released immediately. 3.1.4 standby when fwh4 is high, v ih , the memory is put into standby mode where fwh0-fwh3 are put into a high-impedance state and the supply current is reduced to the standby level, i cc1 . 3.1.5 reset during reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. the memory is in reset mode when interface reset, rp , or cpu reset, init , is low, v il . rp or init must be held low, v il , for t plph . the memory resets to read mode upon return from reset mode and the lock registers return to their default states regardless of their state before reset, see ta b l e 1 0 if rp or init goes low, v il , during a program or erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t plrh to abort a program or erase operation. 3.1.6 block protection block protection can be forced using the signals top block lock, tbl , and write protect, wp , regardless of the state of the lock registers. m50fw040 bus operations 19/53 3.2 address/address multiplexe d (a/a mux) bus operations the address/address multiplexed (a/a mux) interface has a more traditional style interface. the signals consist of a multiplexed address si gnals (a0-a10), data signals, (dq0-dq7) and three control signals (rc , g , w ). an additional signal, rp , can be used to reset the memory. the address/address multiplexed (a/a mux) interface is included for use by flash programming equipment for faster factory programming. only a subset of the features available to the firmware hub (fwh) interface are available; these include all the commands but exclude the security features and other registers. the following operations can be performed using the appropriate bus cycles: bus read, bus write, output disable and reset. when the address/address multiplexed (a/a mux) interface is selected all the blocks are unprotected. it is not possible to protect any blocks through this interface. 3.2.1 bus read bus read operations are used to output the contents of the memory array, the electronic signature and the status register. a valid bus read operation begins by latching the row address and column address signals into the memory using the address inputs, a0-a10, and the row/column address select rc . then write enable (w ) and interface reset (rp ) must be high, v ih , and output enable, g , low, v il , in order to perform a bus read operation. the data inputs/outputs will out put the value, see figure 13 , and ta b l e 2 2 : a / a mux interface read ac characteristics , for details of when the output becomes valid. 3.2.2 bus write bus write operations write to the command interface. a valid bus write operation begins by latching the row address and column address signals into the memory using the address inputs, a0-a10, and the row/ column address select rc . the data should be set up on the data inputs/outputs; output enable, g , and interface reset, rp , must be high, v ih and write enable, w , must be low, v il . the data inputs/outputs are latched on the rising edge of write enable, w . see figure 14: a/a mux interface write ac waveforms , and ta b l e 2 3 : a/a mux interface write ac characteristics , for details of the timing requirements. 3.2.3 output disable the data outputs are high-impedance when the output enable, g , is at v ih . 3.2.4 reset during reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. the memory is in reset mode when rp is low, v il . rp must be held low, v il for t plph . if rp is goes low, v il , during a program or erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to t plrh to abort a program or erase operation. bus operations m50fw040 20/53 figure 6. fwh bus read waveforms table 4. fwh bus read field definitions clock cycle number clock cycle count field fwh0- fwh3 memory i/o description 1 1 start 1101b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh read cycle. 2 1 idsel xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. 3-9 7 addr xxxx i a 28-bit address phase is transferred starting with the most significant nibble first. 10 1 msize 0000b i always 0000b (only single byte transfers are supported). 11 1 tar 1111b i the host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. 12 1 tar 1111b (float) o the fwh flash memory takes control of fwh0- fwh3 during this cycle. 13-14 2 wsyn c 0101b o the fwh flash memory drives fwh0-fwh3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. two wait- states are always included. 15 1 rsyn c 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 data xxxx o data transfer is two clk cycles, starting with the least significant nibble. 18 1 tar 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. 19 1 tar 1111b (float) n/a the fwh flash memory float s its outputs, the host takes control of fwh0-fwh3. ai03437 clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize tar sync data tar 11712322 m50fw040 bus operations 21/53 figure 7. fwh bus write waveforms table 5. fwh bus write field definitions clock cycle number clock cycle count field fwh0- fwh3 memory i/o description 1 1 start 1110b i on the rising edge of clk with fwh4 low, the contents of fwh0-fwh3 indicate the start of a fwh write cycle. 2 1 idsel xxxx i indicates which fwh flash memory is selected. the value on fwh0-fwh3 is compared to the idsel strapping on the fwh flash memory pins to select which fwh flash memory is being addressed. 3-9 7 addr xxxx i a 28-bit address phase is transferred starting with the most significant nibble first. 10 1 msize 0000b i always 0000b (single byte transfer). 11-12 2 data xxxx i data transfer is two cycles, starting with the least significant nibble. 13 1 tar 1111b i the host drives fwh0-fwh3 to 1111b to indicate a turnaround cycle. 14 1 tar 1111b (float) o the fwh flash memory takes control of fwh0- fwh3 during this cycle. 15 1 sync 0000b o the fwh flash memory drives fwh0-fwh3 to 0000b, indicating it has received data or a command. 16 1 tar 1111b o the fwh flash memory drives fwh0-fwh3 to 1111b, indicating a turnaround cycle. 17 1 tar 1111b (float) n/a the fwh flash memory floats its outputs and the host takes control of fwh0-fwh3. ai03441 clk fwh4 fwh0-fwh3 number of clock cycles start idsel addr msize data tar sync tar 11712212 command interface m50fw040 22/53 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. after power-up or a reset operation the memory enters read mode. the commands are summarized in table 7: commands . refer to ta b l e 7 in conjunction with the text descriptions below. 4.1 read memory array command the read memory array command returns the memory to its read mode where it behaves like a rom or eprom. one bus write cycle is required to issue the read memory array command and return the memory to read mode. once the command is issued the memory remains in read mode until another command is issued. from read mode bus read operations will access the memory array. while the program/erase controller is executing a program or erase operation the memory will not accept the read memory array command until the op eration completes. 4.2 read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status r egister command. once the command is issued subsequent bus read operations read the status register until another command is issued. see the section on the status register for details on the definitions of the status register bits. 4.3 read electronic signature command the read electronic signature command is used to read the manufacturer code and the device code. one bus write cycle is required to issue the read electronic signature command. once the command is issued subsequent bus read operations read the manufacturer code or the device code until another command is issued. after the read electronic signature command is issued the manufacturer code and device code can be read using bus read operations using the addresses in ta b l e 6 . m50fw040 command interface 23/53 4.4 program command the program command can be used to program a value to one address in the memory array at a time. two bus write operations are required to issue the command; the second bus write cycle latches the address and data in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. if the address falls in a protected block then the program operation will abort, the data in the memory array will not be ch anged and the stat us register will ou tput the error. during the program operation the memory w ill only accept the re ad status register command and the program/erase suspend comm and. all other commands will be ignored. typical program times are given in ta bl e 1 2 . note that the program command cannot change a bit set at ?0? back to ?1? and attempting to do so will not cause any modification on its va lue. the erase command must be used to set all of the bits in the block to ?1?. see figure 18: program flowchart and pseudo code , for a suggested flowchart on using the program command. 4.5 erase command the erase command can be used to erase a block. two bus write operations are required to issue the command; the second bus write cycle latches the block address in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. if the block is protected then the erase operation will abort, the data in the block will not be changed and the st atus register will output the error. during the erase operation the memory will only accept the read stat us register command and the program/erase suspe nd command. all othe r commands will be ignored. typical erase times are given in ta b l e 1 2 . the erase command sets all of the bits in the block to ?1?. all previous data in the block is lost. see figure 20: erase flowchart and pseudo code , for a suggested flowchart on using the erase command. 4.6 clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to ?0?. one bus write is required to issue the clear status register command. once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to output the same data. the bits in the status register are sticky and do not automatically return to ?0? when a new program or erase command is issued. if an error occurs then it is essential to clear any error bits in the status register by issuing the clear status register command before attempting a new program or erase command. command interface m50fw040 24/53 4.7 program/erase suspend command the program/erase suspend command can be used to pause a program or erase operation. one bus write cycle is required to issue th e program/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit to find out when the program/erase controller has paused; no other commands will be accepted until the pr ogram/erase controller has paused. after the program/eras e controller has paused, the me mory will continue to output the status register until another command is issued. during the polling period between issuing the program/erase susp end command and the program/erase controller pausing it is possible for the operation to complete. once program/erase controller status bit indicates that the program/erase controller is no longer active, the program suspend status bit or the erase suspend status bit can be used to determine if the operation has completed or is suspended. for timing on the delay between issuing the program/erase suspend command and the program/erase controller pausing see ta b l e 1 2 . during program/erase suspend the read memory array, read status register, read electronic signature and pr ogram/erase resume commands will be accepted by the command interface. additionally, if the suspended operation was erase then the program command will also be accepted; only the blocks not being eras ed may be read or programmed correctly. see figure 19: program suspend & resume flowchart and pseudo code , and figure 21: erase suspend & resume flowchart and pseudo code , for suggested flowcharts on using the program/erase suspend command. 4.8 program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the program/erase resume command. once the command is issued subsequent bus read operations read the status register. table 6. read electronic signature code address data manufacturer code 00000h 20h device code 00001h 2ch m50fw040 command interface 25/53 table 7. commands (1) 1. x don?t care, pa program address, pd program data, ba any address in the block. command cycles bus write operations 1st 2nd address data address data read memory array (2) 2. read memory array. after a read memory array command, read the memory as normal until another command is issued. 1 x ffh read status register (3) 3. read status register. after a read status register command, r ead the status register as normal until another command is issued. 1 x 70h read electronic signature (4) 4. read electronic signature. after a read electronic signature command, read manufacturer code, device code until another command is issued. 1 x 90h 1 x 98h program (5) 5. erase, program. after these commands read the status re gister until the command completes and another command is issued. 2 x 40h pa pd 2 x 10h pa pd erase (5) 2 x 20h ba d0h clear status register (6) 6. clear status register. after the clear status register command bits 1, 3, 4 and 5 in the status register are reset to ?0? 1 x 50h program/erase suspend (7) 7. program/erase suspend. after the program/erase suspend co mmand has been accepted, issue read memory array, read status register, program ( during erase suspend) and program/erase resume commands. 1x b0h program/erase resume (8) 8. program/erase resume. after the program/erase resume command the suspended program/erase operation resumes, read the status register until the program/erase controller completes and the memory returns to read mode. 1x d0h invalid/reserved (9) 9. invalid/reserved. do not use invalid or reserved commands. 1 x 00h 1 x 01h 1 x 60h 1x 2fh 1x c0h status register m50fw040 26/53 5 status register the status register provides information on the current or previous program or erase operation. different bits in the status register convey different information and errors on the operation. to read the status register the read status register command can be issued. the status register is automatically read after program, erase and program/erase resume commands are issued. the status register can be read from any address. the status register bits are summarized in status register bits . refer to ta b l e 8 in conjunction with the text descriptions below. 5.0.1 program/erase cont roller status (bit 7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase co ntroller status bit is ?0?, the program/erase controller is active; when the bit is ?1?, the program/erase controller is inactive. the program/erase controller status is ?0? immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is ?1?. during program and erase operation the program/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase controller comple tes the operation and the bit is ?1?. after the program/erase controller completes its operation the erase status, program status, v pp status and block protection status bits should be tested for errors. 5.0.2 erase suspend status (bit 6) the erase suspend status bit indicates that an erase operation has been suspended and is waiting to be resumed. the erase suspend status should only be considered valid when the program/erase controller status bit is ?1? (program/erase controller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is ?0? the program/erase controller is active or has completed its operation; when the bit is ?1? a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the erase suspend status bit returns to ?0?. m50fw040 status register 27/53 5.0.3 erase status (bit 5) the erase status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block and still failed to verify that the block has erased correctly. the erase status bit should be read once the program/erase controller status bit is ?1? (program/erase controller inactive). when the erase status bit is ?0? the memory has successfully verified that the block has erased correctly; when the erase status bit is ?1? the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. once the erase status bit is set to ?1? the it can only be reset to ?0? by a clear status register command or a hardware reset. if it is set to ?1? it should be reset before a new program or erase command is issued, ot herwise the new command will appear to fail. 5.0.4 program status (bit 4) the program status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has programmed correctly. the program status bit should be read once the program/erase controller status bit is ?1? (program/era se controller inactive). when the program status bit is ?0? the memory has successfully verified that the byte has programmed correctly; when the program status bit is ?1? the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has programmed correctly. once the program status bit is set to ?1? it can only be reset to ?0? by a clear status register command or a hardware reset. if it is set to ?1? it should be reset before a new program or erase command is issued, otherwis e the new command will appear to fail. 5.0.5 v pp status (bit 3) the v pp status bit can be used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can occur if v pp becomes invalid during a program or erase operation. when the v pp status bit is ?0? the voltage on the v pp pin was sampled at a valid voltage; when the v pp status bit is ?1? the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected; program and erase operation cannot be performed. once the v pp status bit set to ?1? it can only be reset to ?0? by a clear status register command or a hardware reset. if it is set to ?1? it should be reset before a new program or erase command is issued, otherwis e the new command will appear to fail. status register m50fw040 28/53 5.0.6 program suspend status (bit 2) the program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bit is ?1? (program/erase controller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is ?0? the program/erase controller is active or has completed its operation; when the bit is ?1? a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the program suspend status bit returns to ?0?. 5.0.7 block protection status (bit 1) the block protection status bit can be used to identify if the program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is to ?0? no program or erase operations have been attempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is ?1? a program or erase operation has been attempted on a protected block. once it is set to ?1? the block protection status bit can only be reset to ?0? by a clear status register command or a hardware reset. if it is set to ?1? it should be reset before a new program or erase command is issued, ot herwise the new command will appear to fail. using the a/a mux interface the block protection status bit is always ?0?. 5.0.8 reserved (bit 0) bit 0 of the status register is reserved. its value should be masked. m50fw040 status register 29/53 table 8. status register bits operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 program active ?0? x (1) 1. for program operations durin g erase suspend bit 6 is ?1?, otherwise bit 6 is ?0?. ?0? ?0? ?0? ?0? ?0? program suspended ?1 x (1) ?0? ?0? ?0? ?1? ?0? program completed successfully ?1? x (1) ?0? ?0? ?0? ?0? ?0? program failure due to v pp error ?1? x (1) ?0? ?0? ?1? ?0? ?0? program failure due to block protection (fwh interface only) ?1? x (1) ?0? ?0? ?0? ?0? ?1? program failure due to cell failure ?1? x (1) ?0? ?1? ?0? ?0? ?0? erase active ?0? ?0? ?0? ?0? ?0? ?0? ?0? erase suspended ?1? ?1? ?0? ?0? ?0? ?0? ?0? erase completed successfully ?1? ?0? ?0? ?0? ?0? ?0? ?0? erase failure due to v pp error ?1? ?0? ?0? ?0? ?1? ?0? ?0? erase failure due to block protection (fwh interface only) ?1? ?0? ?0? ?0? ?0? ?0? ?1? erase failure due to failed cell(s) in block ?1? ?0? ?1? ?0? ?0? ?0? ?0? firmware hub (fwh) interface co nfiguration registers m50fw040 30/53 6 firmware hub (fwh) in terface configuration registers when the firmware hub interface is selected several additional registers can be accessed. these registers control the protection status of the blocks, read the general purpose input pins and identify the memory using the electronic signature codes. see ta b l e 9 for the memory map of the configuration registers. 6.1 lock registers the lock registers control the protection status of the blocks. each block has its own lock register. three bits within each lock register control the protection of each block, the write lock bit, the read lock bit and the lock down bit. the lock registers can be read and written, though care should be taken when writing as, once the lock down bit is set, ?1?, further modifications to the lock register cannot be made until cleared, to ?0?, by a reset or power-up. see ta bl e 1 0 for details on the bit definitions of the lock registers. 6.1.1 write lock the write lock bit determines whether the contents of the block can be modified (using the program or erase command). when the write lock bit is set, ?1?, the block is write protected; any operations that attempt to change the data in the block will fail and the status register will report the error. when the write lock bit is reset, ?0?, the block is not write protected through the lock register and may be modified unless write protected through some other means. when v pp is less than v pplk all blocks are protected and cannot be modified, regardless of the state of the write lock bit. if top block lock, tbl , is low, v il , then the top block (block 7) is write protected and cannot be modified. similarly, if write protect, wp , is low, v il , then the main blocks (blocks 0 to 6) are write protected and cannot be modified. after power-up or reset the write lock bit is always set to ?1? (write protected). 6.1.2 read lock the read lock bit determines whether the contents of the block can be read (from read mode). when the read lock bit is set, ?1?, the block is read protected; any operation that attempts to read the contents of the block will read 00h in stead. when the read lock bit is reset, ?0?, read operations in the block return the data programmed into the block as expected. after power-up or reset the read lock bit is always reset to ?0? (not read protected). m50fw040 firmware hub (fwh) interface configuration registers 31/53 6.1.3 lock down the lock down bit provides a mechanism for protecting software data from simple hacking and malicious attack. when the lock down bit is set, ?1?, further modification to the write lock, read lock and lock down bits cannot be performed. a reset or power-up is required before changes to these bits can be made. when the lock down bit is reset, ?0?, the write lock, read lock and lock down bits can be changed. 6.2 firmware hub (fwh) gene ral-purpose input register the firmware hub (fwh) general purpose input register holds the state of the firmware hub interface general purpose input pins, fgpi0-fgpi4. when this register is read, the state of these pins is returned. this register is read-only and writing to it has no effect. the signals on the firmware hub interface general purpose input pins should remain constant throughout the whole bu s read cycle in order to guaran tee that the correct data is read. 6.3 manufacturer code register reading the manufacturer code register returns the manufacturer code for the memory. the manufacturer code for stmicroelectronics is 20h. this register is read-only and writing to it has no effect. 6.4 device code register reading the device code register returns the device code for the memory, 2ch. this register is read-only and writing to it has no effect. 6.5 firmware hub (fwh) gene ral-purpose input register the firmware hub (fwh) general purpose input register holds the state of the firmware hub interface general purpose input pins, fgpi0-fgpi4. when this register is read, the state of these pins is returned. this register is read-only and writing to it has no effect. the signals on the firmware hub interface general purpose input pins should remain constant throughout the whole bu s read cycle in order to guaran tee that the correct data is read. 6.6 manufacturer code register reading the manufacturer code register returns the manufacturer code for the memory. the manufacturer code for stmicroelectronics is 20h. this register is read-only and writing to it has no effect. firmware hub (fwh) interface co nfiguration registers m50fw040 32/53 6.7 device code register reading the device code register returns the device code for the memory, 2ch. this register is read-only and writing to it has no effect. table 9. firmware hub configuration register map mnemonic register name memory address default value access t_block_lk top block lock register (block 7) fbf0002h 01h r/w t_minus01_lk top block [-1] lock r egister (block 6) fbe0002h 01h r/w t_minus02_lk top block [-2] lock r egister (block 5) fbd0002h 01h r/w t_minus03_lk top block [-3] lock r egister (block 4) fbc0002h 01h r/w t_minus04_lk top block [-4] lock r egister (block 3) fbb0002h 01h r/w t_minus05_lk top block [-5] lock r egister (block 2) fba0002h 01h r/w t_minus06_lk top block [-6] lock r egister (block 1) fb90002h 01h r/w t_minus07_lk top block [-7] lock r egister (block 0) fb80002h 01h r/w fgpi_reg firmware hub (fwh) general purpose input register fbc0100h n/a r manuf_reg manufacturer code register fbc0000h 20h r dev_reg device code register fbc0001h 2ch r table 10. lock register bit definitions (1) 1. applies to top block lock register (t_block_lk) an d top block [-1] lock register (t_minus01_lk) to top block [-7] lock register (t_minus07_lk). bit bit name value function 7-3 reserved 2 read- lock ?1? bus read operations in this block always return 00h. ?0? bus read operations in this block return the memory array contents. (default value). 1 lock- down ?1? changes to the read-lock bit and the write-lock bit cannot be performed. once a ?1? is written to the lock-down bit it cannot be cleared to ?0?; the bit is always reset to ?0? following a reset (using rp or init ) or after power-up. ?0? read-lock and write-lock can be changed by writing new values to them. (default value). 0 write- lock ?1? program and erase operations in this block will set an error in the status register. the memory contents will not be changed. (default value). ?0? program and erase operations in this block are executed and will modify the block contents. m50fw040 firmware hub (fwh) interface configuration registers 33/53 table 11. general-purpose input register definition (1) 1. applies to the general purpos e inputs register (fgpi-reg). bit bit name value function 7-5 reserved 4fgpi4 ?1? input pin fgpi4 is at v ih ?0? input pin fgpi4 is at v il 3fgpi3 ?1? input pin fgpi3 is at v ih ?0? input pin fgpi3 is at v il 2fgpi2 ?1? input pin fgpi2 is at v ih ?0? input pin fgpi2 is at v il 1fgpi1 ?1? input pin fgpi1 is at v ih ?0? input pin fgpi1 is at v il 0fgpi0 ?1? input pin fgpi0 is at v ih ?0? input pin fgpi0 is at v il program and erase times m50fw040 34/53 7 program and erase times the program and erase times are shown in ta bl e 1 2 . table 12. program and erase times parameter test condition min typ (1) 1. t a = 25c, v cc = 3.3 v. max unit byte program 10 200 s block program 0.4 5 s block erase v pp = 12v 5% 0.75 8 s v pp = v cc 110s program/erase suspend to program pause (2) 2. sampled only, not 100% tested. 5s program/erase suspend to block erase pause (2) 30 s m50fw040 maximum rating 35/53 8 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 13. absolute maximum ratings symbol parameter min max unit t stg storage temperature ?65 150 c v io (1) 1. minimum voltage may undershoot to ?2v and for less th an 20ns during transiti ons. maximum voltage may overshoot to v cc + 2v and for less than 20ns during transitions. input or output voltage ?0.6 v cc + 0.6 v v cc supply voltage ?0.6 4 v v pp program voltage ?0.6 13 v dc and ac parameters m50fw040 36/53 9 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in ta bl e 1 4 , ta bl e 1 5 and ta b l e 1 6 . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 8. fwh interface ac testing input output waveforms table 14. operating conditions symbol parameter min max unit t a ambient operating temperature (device grade 5) ?20 85 c v cc supply voltage 3 3.6 v table 15. fwh interface ac measurement conditions parameter value unit load capacitance (c l )10pf input rise and fall times 1.4 ns input pulse voltages 0.2 v cc and 0.6 v cc v input and output timing ref. voltages 0.4 v cc v table 16. a/a mux interface ac measurement conditions parameter value unit load capacitance (c l )30pf input rise and fall times 10 ns input pulse voltages 0 to 3 v input and output timing ref. voltages 1.5 v ai03404 0.6 v cc 0.2 v cc 0.4 v cc i o > i lo i o < i lo i o < i lo input and output ac testing waveform output ac tri-state testing waveform m50fw040 dc and ac parameters 37/53 figure 9. a/a mux interface ac testing input output waveform table 17. impedance (1) 1. ta = 25 c, f = 1 mhz). symbol parameter test condition min max unit c in (2) 2. sampled only, not 100% tested. input capacitance v in = 0v 13 pf c clk (2) clock capacitance v in = 0v 3 12 pf l pin (3) 3. see pci specification. recommended pin inductance 20 nh ai01417 3v 0v 1.5v dc and ac parameters m50fw040 38/53 table 18. dc characteristics symbol parameter interface test condition min max unit v ih input high voltage fwh 0.5 v cc v cc + 0.5 v a/a mux 0.7 v cc v cc + 0.3 v v il input low voltage fwh ?0.5 0.3 v cc v a/a mux -0.5 0.8 v v ih (init ) init input high voltage fwh 1.35 v cc + 0.5 v v il (init ) init input low voltage fwh ?0.5 0.2 v cc v i li (2) input leakage current 0v v in v cc 10 a i li2 ic, idx input leakage current ic, id0, id1, id2, id3 = v cc 200 a r il ic, idx input pull low resistor 20 100 k ? v oh output high voltage fwh i oh = ?500 a 0.9 v cc v a/a mux i oh = ?100 av cc ? 0.4 v v ol output low voltage fwh i ol = 1.5ma 0.1 v cc v a/a mux i ol = 1.8ma 0.45 v i lo output leakage current 0v v out v cc 10 a v pp1 v pp voltage 3 3.6 v v pph v pp voltage (fast erase) 11.4 12.6 v v pplk (1) v pp lockout voltage 1.5 v v lko (1) v cc lockout voltage 1.8 2.3 v i cc1 supply current (standby) fwh fwh4 = 0.9 v cc , v pp = v cc all other inputs 0.9 v cc to 0.1 v cc v cc = 3.6v, f(clk) = 33mhz 100 a i cc2 supply current (standby) fwh fwh4 = 0.1 v cc , v pp = v cc all other inputs 0.9 v cc to 0.1 v cc v cc = 3.6v, f(clk) = 33mhz 10 ma i cc3 supply current (any internal operation active) fwh v cc = v cc max, v pp = v cc f(clk) = 33mhz i out = 0ma 60 ma i cc4 supply current (read) a/a mux g = v ih , f = 6mhz 20 ma m50fw040 dc and ac parameters 39/53 1. sampled only, not 100% tested. 2. input leakage currents include high-z output leakage fo r all bidirectional buffers with tri-state outputs. figure 10. fwh interface clock waveform 1. devices on the pci bus must work with any clock frequency between dc and 33mhz. below 16mhz devices may be guaranteed by des ign rather than tested. refer to pci specification. i cc5 (1) supply current (program/erase) a/a mux program/erase controller active 20 ma i pp v pp supply current (read/standby) v pp > v cc 400 a i pp1 (1) v pp supply current (program/erase active) v pp = v cc 40 ma v pp = 12v 5% 15 ma table 19. fwh interface clock characteristics symbol parameter test condition value unit t cyc clk cycle time (1) min 30 ns t high clk high time min 11 ns t low clk low time min 11 ns clk slew rate peak to peak min 1 v/ns max 4 v/ns table 18. dc characteristics (continued) symbol parameter interface test condition min max unit ai03403 thigh tlow 0.6 v cc tcyc 0.5 v cc 0.4 v cc 0.3 v cc 0.2 v cc 0.4 v cc , p-to-p (minimum) dc and ac parameters m50fw040 40/53 figure 11. fwh interface ac signal timing waveforms ai03405 tchqv tchqx tchqz tchdx valid fwh0-fwh3 tdvch clk valid output data float output data valid input data table 20. fwh interface ac signal timing characteristics symbol pci symbol parameter test condition value unit t chqv t val clk to data out min 2 ns max 11 ns t chqx (1) t on clk to active (float to active delay) min 2 ns t chqz t off clk to inactive (active to float delay) max 28 ns t avch t dvch t su input set-up time (2) min 7 ns t chax t chdx t h input hold time (2) min 0 ns 1. the timing measurements for active/fl oat transitions are defined when the curr ent through the pin equals the leakage current specification. 2. applies to all inputs except clk. m50fw040 dc and ac parameters 41/53 figure 12. reset ac waveforms table 21. reset ac characteristics symbol parameter test condition value unit t plph rp or init reset pulse width min 100 ns t plrh rp or init low to reset program/erase inactive max 100 ns program/erase active max 30 s rp or init slew rate (1) 1. see chapter 4 of the pci specification. rising edge only min 50 mv/ns t phfl rp or init high to fwh4 low fwh interface only min 30 s t phwl t phgl rp high to write enable or output enable low a/a mux interface only min 50 s ai03420 rp, init w, g, fwh4 tplph rb tplrh tphwl, tphgl, tphfl dc and ac parameters m50fw040 42/53 figure 13. a/a mux interface read ac waveforms table 22. a/a mux interface read ac characteristics symbol parameter test condition value unit t avav read cycle time min 250 ns t avcl row address valid to rc low min 50 ns t clax rc low to row address transition min 50 ns t avch column address valid to rc high min 50 ns t chax rc high to column address tr a n s i t i o n min 50 ns t chqv (1) 1. g may be delayed up to t chqv ? t glqv after the rising edge of rc without impact on t chqv . rc high to output valid max 150 ns t glqv (1) output enable low to output valid max 50 ns t phav rp high to row address valid min 1 s t glqx output enable low to output tr a n s i t i o n min 0 ns t ghqz output enable high to output hi-z max 50 ns t ghqx output hold from output enable high min 0 ns ai03406 tavav tclax tchax tglqx tglqv tghqx valid a0-a10 g dq0- dq7 rc tchqv tghqz column addr valid w rp tphav row addr valid next addr valid tavcl tavch m50fw040 dc and ac parameters 43/53 figure 14. a/a mux interface write ac waveforms ai04185 tclax tchax twhdx tdvwh valid srd a0-a10 g dq0-dq7 rc tchwh twhrl c1 w r1 tavcl tavch r2 c2 twlwh twhwl rb v pp tvphwh twhgl tqvvpl d in1 d in2 write erase or program setup write erase confirm or valid address and data automated erase or program delay read status register data ready to write another command table 23. a/a mux interface write ac characteristics symbol parameter test condition value unit t wlwh write enable low to write enable high min 100 ns t dvwh data valid to write enable high min 50 ns t whdx write enable high to data transition min 5 ns t avcl row address valid to rc low min 50 ns t clax rc low to row address transition min 50 ns t avch column address valid to rc high min 50 ns t chax rc high to column address transition min 50 ns t whwl write enable high to write enable low min 100 ns t chwh rc high to write enable high min 50 ns t vphwh (1) v pp high to write enable high min 100 ns t whgl write enable high to output enable low min 30 ns t whrl write enable high to rb low min 0 ns t qvvpl (1)(2) output valid, rb high to v pp low min 0 ns 1. sampled only, not 100% tested. 2. applicable if v pp is seen as a logic input (v pp < 3.6v). package mechanical m50fw040 44/53 10 package mechanical figure 15. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package outline 1. drawing is not to scale. table 24. plcc32 ? 32 pin rectangular plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 3.17 3.56 0.125 0.140 a1 1.53 2.41 0.060 0.095 a2 0.38 ? 0.015 ? b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 cp 0.10 0.004 d 12.32 12.57 0.485 0.495 d1 11.35 11.51 0.447 0.453 d2 4.78 5.66 0.188 0.223 d3 7.62 ? ? 0.300 ? ? e 14.86 15.11 0.585 0.595 e1 13.89 14.05 0.547 0.553 e2 6.05 6.93 0.238 0.273 e310.16? ?0.400? ? e1.27? ?0.050? ? f 0.00 0.13 0.000 0.005 r0.89? ?0.035? ? n32 32 plcc-a d e3 e1 e 1 n d1 d3 cp b e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 e2 d2 d2 m50fw040 package mechanical 45/53 figure 16. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package outline 1. drawing is not to scale. table 25. tsop32 ? 32 lead plastic thin small outline, 8x14 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 0 5 0 5 b 0.170 0.270 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 13.800 14.200 0.5433 0.5591 d1 12.300 12.500 0.4843 0.4921 e 0.500 ? ? 0.0197 ? ? e 7.900 8.100 0.3110 0.3189 l 0.500 0.700 0.0197 0.0276 n32 32 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 package mechanical m50fw040 46/53 figure 17. tsop40 ? 40 lead plastic thin small outline, 10x20 mm, package outline 1. drawing is not to scale. table 26. tsop40 ? 40 lead plastic thin small outline, 10x20 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 b 0.170 0.270 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 19.800 20.200 0.7795 0.7953 d1 18.300 18.500 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? e 9.900 10.100 0.3898 0.3976 l 0.500 0.700 0.0197 0.0276 0 5 0 5 n40 40 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 m50fw040 part numbering 47/53 11 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 27. ordering information scheme example: m50fw040 k 5 t g device type m50 architecture f = firmware hub interface operating voltage w = 3v to 3.6v device function 040 = 4 mbit (x8), uniform block package k = plcc32 nb = tsop32 (8 x 14mm) (1) 1. devices delivered in this pack age are not recommended for new design. n = tsop40: 10 x 20 mm (1) device grade 5 = temperature range ?20 to 85 c. device tested with standard test flow option blank = standard packing t = tape & reel packing plating technology p or g = ecopack? (rohs compliant) flowcharts and pseudo codes m50fw040 48/53 12 flowcharts and pseudo codes figure 18. program flowchart and pseudo code 1. a status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation by followi ng the correct command sequence. 2. if an error is found, the status register must be cleared before further pr ogram/erase controller operations. write 40h or 10h ai03407 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program command: ? write 40h or 10h ? write address & data (memory enters read status state after the program command) do: ?read status register if program/erase suspend command given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: ? error handler if b4 = 1, program error: ? error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: ? error handler suspend suspend loop no yes fwh interface only m50fw040 flowcharts and pseudo codes 49/53 figure 19. program suspend & resume flowchart and pseudo code write 70h ai03408 read status register yes no b7 = 1 yes no b2 = 1 program continues write a read command program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 1 if b2 = 0 program completed write d0h program/erase resume command: ? write d0h to resume the program ? if the program operation completed then this is not necessary. the device returns to read as normal (as if the program/erase suspend was not issued). read data from another address start write b0h program complete write ffh read data flowcharts and pseudo codes m50fw040 50/53 figure 20. erase flowchart and pseudo code 1. if an error is found, the status register must be cleared before further pr ogram/erase controller operations. write 20h ai03409 start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error (1) erase command: ? write 20h ? write block address & d0h (memory enters read status register after the erase command) do: ? read status register ? if program/erase suspend command given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: ? error handler if b4, b5 = 1, command sequence error: ? error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: ? error handler end yes no b1 = 0 erase to protected block error (1) if b1 = 1, erase to protected block error: ? error handler yes fwh interface only m50fw040 flowcharts and pseudo codes 51/53 figure 21. erase suspend & resume flowchart and pseudo code write 70h ai03410 read status register yes no b7 = 1 yes no b6 = 1 erase continues program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 1 if b6 = 0, erase completed write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: ? write d0h to resume erase ? if the erase operation completed then this is not necessary. the device returns to read as normal (as if the program/erase suspend was not issued). revision history m50fw040 52/53 13 revision history table 28. document revision history date version changes september 2000 -01 first issue 04-oct-2000 -02 dc characteristics: i cc4 changed 11-apr-01 -03 document type: from preliminary data to data sheet program and erase functions clarification read electronic signature table change fwh register configuration map table change input register definition table, note clarification dc characteristics parameters clarification and new v ih and v il parameters added fwh interface ac signal timing characteristics change a/a mux interface read ac characteristics change a/a mux interface write ac characteristics change a/a mux interface write ac waveforms change 06-jul-2001 -04 note 2 changed ( table 13: absolute maximum ratings ) 12-mar-2002 -05 rfu pins must be left disconnected specification of plcc32 package mechanical data revised 09-jul-2004 6.0 revision numbering modified. document imported in new template (and so reformatted). temperature range ordering information replaced by device grade, standard packing option added and plating technology added to table 27: ordering information scheme . t lead parameter added to table 13: absolute maximum ratings and t bias parameter removed. 12-jul-2004 7.0 inches values corrected in table 27: ordering information scheme . 10-nov-2004 8.0 tsop32 package added. figure 2: logic diagram (a/a mux interface) and table 2: signal names (a/a mux interface) added. 24-oct-2006 9 document converted to new st template. packages are ecopack? compliant. t lead removed from ta b l e 1 3 : absolute maximum ratings . device grade 1 removed. blank plating technology option removed from table 27: ordering information scheme . m50fw040 53/53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
Price & Availability of M50FW040N5G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |